2018 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 5-8, 2018Hilton San Diego Resort & Spa San Diego, CA

Sweet Memories of Deep Learning

Tue, 2018-08-14 03:51 -- root
Who doesn't remember the basics of deep learning! But can you design systems for in-memory computing using FeFETs that reduce power consumption and ReRAM that moderates data migration? The first paper in this session investigates reliable ReRAM-based deep learning with single-bit cells. The second paper introduces a power-efficient FeFET-based in-memory computing architecture, whereas the third paper designs and implements a system for multitask (transfer) learning using GPUs and ReRAM. Even as you learn new things, important information should stay in your memory!

Generate, Stimulate and Simulate!

Tue, 2018-08-14 03:51 -- root
Effective generation of stimuli is a critical step in the verification flow. The three papers in this session present advances in this field. The first paper is focused on coverage-directed testing in FPGA environments using the insights developed in software verification. The second paper speeds the generation of directed tests for shared-memory multi-processor verification. The third paper presents a method that facilitates rapid generation of multiple and diverse stimuli from complex constraints.

EDA for Cyber-Physical Systems

Tue, 2018-08-14 03:51 -- root
From automating tasks in the domain of integrated circuits design, Electronic Design Automation (EDA) has been moving up the design abstraction ladder, now encompassing many system-level design tasks. The next challenge facing the EDA community is to develop methods and also tools for cyber-physical systems (CPS) design. However, currently available EDA tools and methods cannot handle these complex CPSs where the physical processes, the control algorithms and the computation and communication platforms are all modeled and designed in a tightly integrated fashion.

Architecting for Efficiency of Deep Learning

Tue, 2018-08-14 03:51 -- root
The papers of this session aim to improve the efficiency of deep learning systems via optimizing the architecture for hardware, algorithm, and design methodology. The first two papers propose new hardware architecture for deep neural network accelerators. The third paper designs a new neural network architecture for energy-constrained applications. The fourth paper presents neural network-based design methodology for timing error prediction.

Accelerated Safe and Secure Machine Learning

Tue, 2018-08-14 03:51 -- root

This tutorial brings the top experts from the industry and academia to cover several important topics in safe, and secure machine learning that enable automated synthesis of trustworthy machine learning for the state-of-the-art algorithms. The discussed topics include ML on private (encrypted) data, model assurance against the contemporary attacks including adversarial learning and transfer learning, IP protection for ML, as well as trusted execution of contemporary ML algorithms.

Emerging Reconfigurable Nanotechnologies: Can they Support Future Electronics ?

Tue, 2018-08-14 03:51 -- root
Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the freedom to choose between p- and n-type functionality from a single transistor. In order to optimally utilize the feature-sets of these technologies, circuit designs and storage elements require novel design to complement the existing and future electronic requirements. An important aspect to sustain such endeavors is to supplement the existing design flow from the device level to the circuit level. This should be backed by a thorough

Flexibility Makes Learning Better

Tue, 2018-08-14 03:51 -- root
Efficient training and deployment of neural networks are critical. The first paper in this session discusses a novel quantization scheme using powers-of-arbitrary-log-bases, and the second paper presents a processing in-DRAM framework for binary CNNs. The third paper proposes AXNet, a neural network based approximate computing allowing holistic end-to-end training. The last paper in this session proposes a scalable-effort CNN (ConvNet) that allows effort-accuracy scalability for classification of data at multi-level abstraction.

Ahoy! Anti-piracy Techniques

Tue, 2018-08-14 03:51 -- root
Piracy attacks have been threatening the IC industry. This session explores the new territories of trusted manufacturing in reversible computing, 3D ICs, analog mixed-signal, and timing countermeasures. The first paper explains how reversible circuits can be used to prevent piracy and reverse engineering. The second paper proposes an attack on timing locks. The third one extends the boundary of logic locking to analog and mixed-signal systems, and the last paper solves split manufacturing and camouflaging problems in 3D systems.

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