2018 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 5-8, 2018Hilton San Diego Resort & Spa San Diego, CA

Routing: The Devil is in the Details

Tue, 2018-08-14 03:51 -- root
Continuous technology node shrinking and the increased complicated design rules have made detailed routing one of the most contentious parts of the physical design. In this session, the first paper discusses machine learning based routing congestion and violation prediction methods. This is followed by two papers on initial detailed routing. The session concludes with a paper on an open net locator for ECO routing.

Majority Logic Synthesis

Tue, 2018-08-14 03:51 -- root
The majority function xyz evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades.

Is Adversarial Learning a Threat for Machine Learning? Defense Strategies and Design of Better Machine Learners!

Tue, 2018-08-14 03:51 -- root

In the recent years, Machine Learning (ML) especially mammalian brain inspired neural networks (including deep neural networks (DNNs)) have demonstrated an impressive performance and robustness to noise in different domains ranging from medical imaging, autonomous driving to defense applications. Despite DNNs being robust to noise and perturbations, recent research works have exploited the vulnerabilities and showed that the DNNs can be fooled by adding specially crafted perturbations to the input.

Biochips, Blockchain, and Learning in CPS

Tue, 2018-08-14 03:51 -- root
Cyber-Physical Systems serve as the fabric of modern and future intelligent world. The first two papers of the session covers Artificial Neural Networks as enabler for CPS, one on the hardening of deep neural networks against adversarial attacks, and the other on reinforcement learning for wearable devices. The third and fourth papers are on two emerging applications of CPS, biochips and blockchain.

Post-CMOS Technologies and Emerging Applications

Tue, 2018-08-14 03:51 -- root
This session covers the post-CMOS technologies and the related emerging applications. The resistive memory (memristor) device is proposed as the enabling technology for main memory, routing switch in FPGA, and synaptic weight in neural network accelerators. An Ising processor with approximated parallel tempering is proposed to improve the quality of optimization solutions.

Deep Dive into Mixed Size Cell Placement

Tue, 2018-08-14 03:51 -- root
In the physical design placement implementation flow, mixed-height cells introduce additional challenges, such as Poly-alignment, fence regions, multi-cell spacing, and technology constraints. In this session, the first paper addresses the challenges involving the multi-cell spacing constraint. The remaining three papers address the problems related to technology and fence region constraints.

Managing Heterogeneous Many-cores for High-Performance and Energy-Efficiency

Tue, 2018-08-14 03:51 -- root

Heterogeneity has become the Swiss army knife for designing energy-efficient and thermally safe systems ranging from simple edge devices to high-performance multi-core processing platforms. Integration of application-specific heterogeneous accelerators and general-purpose cores deliver programmable systems-on-chip (SoCs) with superior performance and significantly lower power footprint compared to homogenous architectures.

Hardware Intellectual Property (IP) Protection Techniques: What, when, and how to use?

Tue, 2018-08-14 03:51 -- root
Globalization of Integrated Circuit (IC) design is forcing the IC/ IP designers and users re-assess their trust in hardware. As the IC design flow spans the globe, driven by cost-conscious consumer electronics, hardware is increasingly prone to new kinds of attacks such as counterfeiting, hardware Trojans, side channel analysis, reverse engineering and IP piracy.


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