2018 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 5-8, 2018Hilton San Diego Resort & Spa San Diego, CA

Synthesizing Neural, Parallel, and Approximate Logic

Tue, 2018-08-14 03:51 -- root
The emergence of machine learning and artificial intelligence presents new challenges to hardware design and synthesis. In this session, the first two papers present the synthesis of logic originated from neural networks: with binary weights or threshold logic. The third paper discusses the use of approximate computing in logic optimization with delay-driven approximate synthesis framework. The last paper demonstrates how to accelerate logic synthesis with AIG rewriting.

Routing: The Devil is in the Details

Tue, 2018-08-14 03:51 -- root
Continuous technology node shrinking and the increased complicated design rules have made detailed routing one of the most contentious parts of the physical design. In this session, the first paper discusses machine learning based routing congestion and violation prediction methods. This is followed by two papers on initial detailed routing. The session concludes with a paper on an open net locator for ECO routing.

Majority Logic Synthesis

Tue, 2018-08-14 03:51 -- root
The majority function evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority function in the last volume of his seminal The Art of Computer Programming as “probably the most important ternary operation in the entire universe.” Majority logic sythesis has recently regained signficant interest in the design automation community due to nanoemerging technologies which operate based on the majority function.

Is Adversarial Learning a Threat for Machine Learning? Defense Strategies and Design of Better Machine Learners!

Tue, 2018-08-14 03:51 -- root
In the recent years, Machine Learning (ML) especially mammalian brain inspired neural networks (including deep neural networks (DNNs)) have demonstrated an impressive performance and robustness to noise in different domains ranging from medical imaging, autonomous driving to defense applications. Despite DNNs being robust to noise and perturbations, recent research works have exploited the vulnerabilities and showed that the DNNs can be fooled by adding specially crafted perturbations to the input. In this session, first talk will introduce the challenges of ML in adversarial settings.

Biochips, Blockchain, and Learning in CPS

Tue, 2018-08-14 03:51 -- root
Cyber-Physical Systems serve as the fabric of modern and future intelligent world. The first two papers of the session covers Artificial Neural Networks as enabler for CPS, one on the hardening of deep neural networks against adversarial attacks, and the other on reinforcement learning for wearable devices. The third and fourth papers are on two emerging applications of CPS, biochips and blockchain.

Post-CMOS Technologies and Emerging Applications

Tue, 2018-08-14 03:51 -- root
This session covers the post-CMOS technologies and the related emerging applications. The resistive memory (memristor) device is proposed as the enabling technology for main memory, routing switch in FPGA, and synaptic weight in neural network accelerators. An Ising processor with approximated parallel tempering is proposed to improve the quality of optimization solutions.

Deep Dive into Mixed Size Cell Placement

Tue, 2018-08-14 03:51 -- root
In the physical design placement implementation flow, mixed-height cells introduce additional challenges, such as Poly-alignment, fence regions, multi-cell spacing, and technology constraints. In this session, the first paper addresses the challenges involving the multi-cell spacing constraint. The remaining three papers address the problems related to technology and fence region constraints.

Managing Heterogeneous Many-Cores for High-Performance and Energy-Efficiency

Tue, 2018-08-14 03:51 -- root
Heterogeneity has become the Swiss army knife for designing energy-efficient and thermally safe systems ranging from simple edge devices to high-performance multi-core processing platforms. Integration of application-specific heterogeneous accelerators and general-purpose cores deliver programmable systems-on-chip (SoCs) with superior performance and significantly lower power footprint compared to homogenous architectures.

Analyzing the Disruptive Impact of a Silicon Compiler

Tue, 2018-08-14 03:51 -- root
Recent years have seen an explosion in the cost and time required to design advanced System-on-Chips (SoCs), systems-in-packages (SiPs), and PCBs. As part of the $1.5B Electronics Resurgence Initiative (ERI), DARPA is building the world's first general purpose silicon compilers. The effort involves two distinct research programs, the Intelligent Design of Electronic Assets (IDEA) program aiming to create a no-human-in-the-loop layout generator for digital and analog circuits, and the Posh Open Source Hardware (POSH) program aiming to create a high quality trustable open source ecosystem.


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