Medical Cyber-Physical Systems are safety-critical interconnected, intelligent systems of medical devices and applications, and have witnessed breakthroughs in interacting with patients in medical and healthcare. Originally, medical CPS design is a cross-layer effort requiring expertise from completely different fields: from high level models and treatment guidelines, implemented by software code and protocols, running on hardware platforms. These multiple layers of abstraction with well-defined interfaces allow these groups to work independently.
This session focuses on the recent advances enabled by resistive random-access memory (RRAM) technology -- that could help to overcome the "memory wall" associated with von Neumann computing architectures. Papers in this session will consider memristive crossbar devices and their applications to routing, neuromorphic systems, weight stability, and perceptron classifiers.
From ASICs to FPGAs, this session showcases the heterogeneous nature of placement to handle the critical issue of routing congestion. The first two papers perform macro-block placement to address routing challenges. The third paper proposes a new clustering approach for lithography hotspot pattern classification, and the final paper describes a clock-aware placement algorithm for large-scale heterogeneous FPGAs.
Efficient power and thermal modeling is key for designing high performance chips without breaking the cooling limits. This session looks into power and thermal management at various level of granularity. The first paper deals with managing workload so that the supply voltage variation remains within the specified limit. The second paper exploits unique thermal characteristics of STTMRAM for energy efficiency. Thermal management of mobile SoCs is the focus of the third paper and the final paper introduces a computationally-efficient thermal modeling methodology.
This session has four papers that contribute new advances in approximating and neural networks. The first paper presents a new technique to approximate mathematical functions using Taylor series and look-up tables. The second paper proposes a novel method to generate approximate data processing given arbitrary data flow graphs as inputs. The third paper presents a new spiking neural network model and a back-propagation algorithm with much improved accuracy.
This session addresses a range of synthesis problems that span clockless paradigm, approximate computing, datapath optimization, and accurate modeling of HLS-generated accelerators. The first paper proposes a new framework for improving quality of asynchronous circuits leveraging a suite of existing tools. The paper on the approximate computing presents a new method synthesizing arithmetic circuits. The third paper exploits graph isomorphism to achieve more efficient resource sharing at bit-level.
Field Programmable Gate Arrays (FPGA) finds wider applications nowadays with the advancement in technology and gains increasing interests in heterogeneous computing and energy efficiency acceleration. FPGAs have evolved from simple programmable logic fabrics to replacing custom designs and processors for signal processing and other wide spreading applications. New generations of FPGA target at implementing the whole system on a single device, and various resources like LUT, flip-flop, RAM, DSP, as well as CPUs are placed at different locations of the device.
Robotics is booming all around us. A field that was originally driven by the desire to automate physical work is now raising concerns about the future of work. Less discussed but no more important are the implications on human health, as the science on longevity and resilience indicates that having the drive to work is key for health and wellness. However, robots, machines that were originally invented to automate work, are also becoming helpful by not doing any physical work at all, but instead by motivating and coaching us to do our own work, based on evidence from neuroscience and behavi
This session highlights three emerging topics in software and embedded security. It kicks off with a remote attestation technique that allows a trusted party to verify the integrity of the software running on a remote and potentially compromised device. This is followed by a security validation approach for Systems-on-Chips using static information flow analysis to detect data leakage, untrusted access, confidentiality and integrity. Finally, an approach to memory access control using self-verified address spaces is presented.
This session focuses on the use of machine intelligence to improve the energy efficiency and performance of IoT and wearable devices. The first paper, "Learn-on-the-go", uses transfer learning to improve the classification accuracy through the collaboration of multiple wearable IoT devices. The second paper proposes a method for optimal energy allocation for energy-harvested wearable devices. The third paper uses Q-learning to achieve optimal checkpointing of intermittently-powered IoT devices.