2018 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 5-8, 2018Hilton San Diego Resort & Spa San Diego, CA

Superconducting Electronics Design Automation (S-EDA): Recent Developments and Upcoming Challenges

Tue, 2018-08-14 03:51 -- root
The special session offers attendees an opportunity to bridge the semiconductor ICs/system
technology with the superconducting electronics and quantum computing technologies. The special
session will first describe the most ambitious development program for superconducting electronics
circuit design tools to date—the Intelligence Advanced Research Projects Activity (IARPA)
SuperTools Program—and provide a comprehensive overview of the state of design tool
development as well as the circuit technology in the superconducting electronics community.

When Design Space Exploration Meets with Modern Applications and Systems

Tue, 2018-08-14 03:51 -- root
This session explores the design space of application-specific systems in the format of networks-for-chiplet, networks-on-chip, and FPGAs. The first two papers focus on networks, one optimizes the network design in 2.5D systems across logical, physical, and circuit layers, while the other explores the design space of application-specific NoCs with Monte Carlo Tree Search and Markov models. The last two papers center on FPGAs.

Computationally Efficient and Uncertainty Aware Analog and Mixed-Signal CAD

Tue, 2018-08-14 03:51 -- root
This session covers novel algorithms and design trends of analog/RF/mixed-signal circuits and systems. The first two papers discuss uncertainty qualification theory and machine learning techniques to significantly decrease computational complexity through sample reduction. The next paper addresses the numerical stability in transient circuit simulation. The final paper optimizes the topology of an optical network on chip.

The Future is What You Make It: EDA in the Post-Moore Age

Tue, 2018-08-14 03:51 -- root

Electronic design, design automation and technology have always been linked, but as time progresses and layers of abstraction develop holes or outright crumble, the connections between them necessarily become tighter. It’s not enough to ask how future technology will shape EDA, we also need to ask how EDA will shape technology. The EDA tools of the future will need to deal with heterogenous systems that span more than a single die. They will also need to cover abstractions from device through application software.

Networking Reception

Tue, 2018-08-14 03:51 -- root
Whatever your goal, networking receptions are the perfect venue for you to expand your network and keep you connected! Join us today to catch up with your colleagues and discuss the day's presentations with the conference presenters. All attendees are invited.

The Need and Opportunities of Electromigration-Aware Integrated Circuit Design

Tue, 2018-08-14 03:51 -- root

Electromigration (EM) is becoming a progressively intractable design challenge due to increased interconnect current densities. It has changed from something designers “should” think about to something they “must” think about, i.e. become a requirement. The International Roadmap for Devices and Systems (IRDS) and the International Technology Roadmap for Semiconductors (ITRS) predict that semiconductor scale and interconnect cross-sections in semiconductor technologies will decrease further over the coming years.

Security for Next-Generation Connected and Autonomous Vehicles

Tue, 2018-08-14 03:51 -- root
Next-generation vehicles will perform autonomous and semi-autonomous functions via multi-modal sensing, real-time computation with machine learning techniques, in-vehicle communication using new bus protocols, and control of mechanical components. They will also commutate with other surrounding vehicles and infrastructures via vehicular ad-hoc networks (VANETs) to further improve vehicle safety and transportation efficiency.

Build a Fort: Designing and Assessing Secure Architectures

Tue, 2018-08-14 03:51 -- root
Fixing the security bugs post-deployment is impractical. This section explores novel solutions in assessing the security of a design and building secure architectures, which can be leveraged during design time. The first paper strengthens high-level synthesis tools to verify security properties. The second paper speeds up hardware security verification. The third paper builds a trusted architecture for heterogeneous systems. The final paper utilizes split manufacturing to thwart Trojans.

Synthesizing Neural, Parallel, and Approximate Logic

Tue, 2018-08-14 03:51 -- root
The emergence of machine learning and artificial intelligence presents new challenges to hardware design and synthesis. In this session, the first two papers present the synthesis of logic originated from neural networks: with binary weights or threshold logic. The third paper discusses the use of approximate computing in logic optimization with delay-driven approximate synthesis framework. The last paper demonstrates how to accelerate logic synthesis with AIG rewriting.


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