2018 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 5-9, 2018Hilton San Diego Resort & Spa San Diego, CA

Tue, 2017-08-29 15:54 -- root
The continued down-scaling of nanoscale integrated circuits (IC) presents significant challenges with respect to manufacturability, reliability, cost, and power consumption. Recent work has therefore advanced the concept of “upscaling” through three-dimensional (3D) stacked ICs. Industry trends highlight the viability of 3D integration in actual products (e.g., the AMD Radeon R9 Fury X graphics card, Xilinx Virtex-7 2000T/H580T and Ultra-scale FPGAs). Flash memory vendors have announced multiple layers of memory in a single package, e.g., as many as 32 and 48 layers of Flash memory (Toshiba BiCS). Moore’s law is now entering a new phase characterized by vertical integration (“3D Power Scaling” in the ITRS2.0 2015 report). Today’s 3D integration technology is primarily based on die/wafer stacking since it does not require major changes to the existing fabrication flow or retooling of fabrication processes. However, the increase in fabrication cost (foundries report that TSV processing adds 10% to the wafer cost), the keep-out-zone (KOZ) required for TSVs, and limitations on the die alignment precision impose limits on the device integration density that can be achieved using TSV-based 3D stacking. For example, it has been reported that a minimum KOZ of 3 μm is required for ICs fabricated at the 20 nm technology node and the die alignment precision is imited to 0.5 μm. Newer technologies for 3D integration are therefore being explored to exploit up-scaling to the fullest possible extent. This special session will present a vision into the future of 3D integration. Speakers will address emerging directions in 3D integration techniques and challenges beyond traditional TSV-based 3D integration. Specific topics to be covered include monolithic 3D integration, long-term reliability assessment and design for reliability of interconnects in next-generation 3D ICs, wireless 3D interconnects, and on-chip silicon-photonics 3D interconnects. Each presentation will provide technology overview, describe design, test, and reliability challenges, and highlight recent advances. Attendees will get holistic insights through lively presentations that will encapsulate the latest cutting-edge research in these emerging topics. This session will inform and inspire academic researchers as well as industry practitioners towards new innovations in these directions.
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Special Session
Salons B2 & C
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Monday, November 13, 2017 -
14:00 to 16:00
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