2018 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 5-9, 2018Hilton San Diego Resort & Spa San Diego, CA

Tue, 2017-08-29 15:54 -- root
This session presents a range of SAT-based techniques to conquer major challenges in pre-silicon, post-silicon, repair and functional timing. The first paper proposes a novel approach for SAT-based model checking using approximations. The second paper introduces an approach for improving the coverage of electrical bugs in post silicon validation. The third paper formulates the problem of patching sequential circuits in the presence of retiming and resynthesis. The final paper in the session accelerates functional timing analysis by removing redundancies from the CNF formula that describes the functional and timing constraints on a path.
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Regular Session
Salon E
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Monday, November 13, 2017 -
14:00 to 16:00
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