Qinru Qiu - Syracuse University, USA
Yingyan Lin - Rice University, USA
Chenchen Liu - University of Maryland, USA
In recent years, machine/deep learning algorithms has unprecedentedly improved the accuracies in practical
recognition and classification tasks, some even surpassing human-level accuracy. While significant progresses
have been made on accelerating the models for real-time inference on edge and mobile devices, the training of
the models largely remains offline on server side. State-of-theart learning algorithms for deep neural
networks (DNN) imposes significant challenges for hardware implementations in terms of computation, memory,
and communication. This is especially true for edge devices and portable hardware applications, such as
smartphones, machine translation devices, and smart wearable devices, where severe constraints exist in
performance, power, and area.
There is a timely need to map the latest complex learning algorithms to custom hardware, in order to achieve
orders of magnitude improvement in performance, energy efficiency and compactness. Exemplary efforts from
industry and academia include many application-specific hardware designs (e.g., xPU, FPGA, ASIC, etc.).
Recent progress in computational neurosciences and nanoelectronic technology, such as emerging memory
devices, will further help shed light on future hardwaresoftware platforms for learning on-a-chip. At
the same time new learning algorithms need to be developed to fully explore the potential of the hardware
The overarching goal of this workshop is to explore the potential of on-chip machine learning, to reveal
emerging algorithms and design needs, and to promote novel applications for learning. It aims to establish
a forum to discuss the current practices, as well as future research needs in the aforementioned fields.