2019 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 4-7, 2019The Westin Westminster Westminster, CO



Paper ID  Paper Title
2 Tagged Sentential Decision Diagrams: Combining Standard and Zero-suppressed Compression and Trimming Rules
5 PURE: Using Verified Remote Attestation to Obtain Proofs of Update, Reset and Erasure in Low-End Embedded Systems
15 EISC: An Open-Source System-Level Emulation Platform for FPGA-Based In-storage Computing
28 Power Grid Fixing for Electromigration-induced Voltage Failures
49 A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm
60 ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms
63 Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration
65 Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines
74 Global routing on rhomboidal tiles
75 SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator
82 MAGNet: A Modular Accelerator Generator for Neural Networks
90 FastWave: Accelerating Autoregressive Convolutional Neural Networks on FPGA
99 Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models
100 NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations
104 Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning
111 Efficient Performance Trade-off Modeling for analog circuit based on Bayesian Neural Network
114 A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS
117 Embedding Binary Perceptrons in FPGA to improve Area, Power, and Performance
119 ROAD: Improving Reliability of Multi-core Systems via Asymmetric Aging
128 4D-CGRA : Introducing the branch dimension to spatio-temporal application mapping of CGRAs
131 A Statistical Timing Model for Low Voltage Design Considering Process Variation
132 Multiversion Concurrency Control on Intermittent Systems
138 Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems
146 HAML-SSD: A Hardware Accelerated Hotness-Aware Machine Learning based SSD Management
147 ``IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop
155 Tucker Tensor Decomposition on FPGA
158 GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization
165 Efficient Uncertainty Modeling for System Design via Mixed Integer Programming
169 Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits
173 elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs
176 INA: Incremental Network Approximation Method for Limited Precision Deep Neural Networks
177 Flip-flop State Driven Clock Gating: Concept, Design, and Methodology
181 A Novel Macro Placement Approach based on Simulated Evolution Algorithm
192 Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality
195 BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks
196 Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method
197 Exploiting Randomness in Stochastic Computing
199 Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms
200 Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density
201 ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations
202 Adar: Adversarial Activity Recognition in Wearables
208 Accelerating garbage collection for 3D MLC flash memory with SLC blocks
210 SemiHD: Semi-Supervised Learning Using Hyperdimensional Computing
219 eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators
224 Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption
229 Multi-Stage Optimization for Energy-Efficient Active Cell Balancing in Battery Packs
230 Time-Frame Folding: Back to the Sequentiality
233 Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access
237 A General Logic Synthesis Framework for Memristor-based Logic Design
241 Karna: A gate-sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection
243 An Agile Precision-Tunable CNN Accelerator based on ReRAM
244 SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power based Side Channel Attacks
245 VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips
246 ACG-Engine: An Inference Accelerator for Content Generative Neural Networks
248 Global Interconnect Optimization
250 Endurance Enhancement of Multi-Level Cell Phase Change Memory
258 Clock gating synthesis of netlist with cyclic logic paths
261 A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks
266 A Uniform Modeling Methodology for Benchmarking DNN Accelerators
279 Automated Probe Repositioning for On-Die EM Measurements
281 An Energy-efficient Processing-in-Memory Architecture for Recurrent Neural Networks in a Spin Orbit Torque MRAM
290 The role of multiplicative complexity in compiling low T-count oracle circuits
292 Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design Verification
299 [Anon.]: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction
300 Re-Tangle: ReRAM-based Processing-in-Memory Architecture for Transaction-based Blockchain
313 How to Efficiently Handle Complex Values? Implementing Decision Diagrams for Quantum Computation
323 Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs
327 WCET Guarantees for Opportunistic Runtime Reconfiguration
328 Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs
334 Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes
335 Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs
339 Timing-Aware Fill Insertions with Design-Rule and Density Constraints
341 Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders
349 Toward Instantaneous Sanitization through Disturbance-induced Errors and Recycling Programming over 3D Flash Memory
352 An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology
355 Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly
367 ALWANN: Automatic Layer-Wise Approximation of Deep Neural Network Accelerators without Retraining
379 Task Mapping-Assisted Laser Power Scaling for Optical Network-on-Chips
382 Strengthening PUFs using Composition
388 An Event-driven Neuromorphic System with Biological Plausible Temporal Dynamics
408 Holistic Power Side-Channel Leakage Assessment: Towards a Robust Multidimensional Metric
410 Towards HDL-based Synthesis of Reversible Circuits with No Additional Lines
414 SPRoute: A Scalable Parallel Negotiation-based Global Router
421 Understanding and Exploiting the Internals of GPU Resource Allocation for Critical Systems
424 Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices
431 PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design
442 GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance
445 A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors
448 CHASE: A Configurable Hardware-Assisted Security Extension for Real-Time Systems
449 Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs
460 Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning
466 Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks
478 IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits
507 GenUnlock: An Automated Genetic Algorithm Framework for Unlocking Logic Encryption