Tuesday, November 3, 2009
  Monday | Tuesday | Wednesday

  Registration - 7:30am - 6:00pm (Bayshore Foyer)
Speakers’ Breakfast
- 7:30am (Siskiyou Ballroom)
  Oak Ballroom Fir Ballroom Pine Ballroom Cedar Ballroom Donner Ballroom


Session 4A

Tutorial: Introduction to GPU Programming for EDA

Session 4B

Analytical Advances in Physical Synthesis

Session 4C

Thermal-Aware Management Techniques for Multi-Core Architectures

Designer Track:

When SPICE is not Enough

Session 4E

Tutorial: Analysis and Testing of Concurrent Programs

Coffe Break - 10:00 - 10:30am


Session 5A

Statistical Timing Analysis and Its Application

Session 5B

Congestion Driven Placement

Session 5C

New Applications in Logic Synthesis

Designer Track:

Practical Experience and Future Tool Directions at New Process Nodes

Sponsored By:Lunch Presentation: Smart Grid for the 21st Century: 12:00 - 1:15pm


Session 6A

Advanced Modeling and Simulation Methods

Session 6B

Characterization and Compensation of Variability

Session 6C

Policies and Methods for Low Power

Session 6D

Emerging Memory Technologies

Session 6E

Special Session:   Power 7 - Verification challenges of a High-End 8-Core Microprocessor

Coffee Break: 3:30- 4:00pm


Session 7A

Advanced Device Reliability and Modeling

Session 7B

Clock Optimization and Parallel Algorithm in EDA

Session 7C

Analysis and Optimization of Network-On-Chip and Multiprocessor SoC

Session 7D

Design-Patterning Interactions

Session 7E

Special Session: Statistical Timing: Where is the Tofu?

ICCAD RECEPTION: 6:00 - 8:00pm
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