2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

Tue, 2017-08-29 15:54 -- root
From ASICs to FPGAs, this session showcases the heterogeneous nature of placement to handle the critical issue of routing congestion. The first two papers perform macro-block placement to address routing challenges. The third paper proposes a new clustering approach for lithography hotspot pattern classification, and the final paper describes a clock-aware placement algorithm for large-scale heterogeneous FPGAs.
Event ID: 
b81c5317-2ced-4982-81f1-6f8c513458ac
Event Type: 
Regular Session
Location: 
Salons A & B1
Event Time: 
Tuesday, November 14, 2017 -
16:15 to 18:15
Session Number: 
7
Session Number Suffix: 
A
Session Number: 
7
confID: 
242