2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

2017 CAD Contest at ICCAD

Tue, 2017-08-29 15:54 -- root
The CAD Contest at ICCAD is a challenging, multi-month R&D competition, focusing on modern and practical problems at the forefront of Electronic Design Automation (EDA). In its sixth year, the 2017 CAD Contest at ICCAD is among the premier worldwide academic programming contests, attracting 122 teams from 10 different regions/countries. This year, three contest problems in the areas of ECO logic synthesis, ECO routing and placement legalization for the advanced nodes are called for competition.

AI for CPS: Machine Learning for Intelligent and Secure Cyber-Physical Systems

Tue, 2017-08-29 15:54 -- root
With the proliferation of sensor data and advancement of processing power, machine learning techniques have shown great promise in cyber-physical systems (CPS) applications. These techniques are particularly effective for analyzing, controlling and optimizing complex CPS where the system dynamics and surrounding environment are hard to capture; however, applying them in practical systems often faces challenges from resource and timing constraints as well as reliability, predictability and security requirements.

3D Integration Beyond TSVs

Tue, 2017-08-29 15:54 -- root
The continued down-scaling of nanoscale integrated circuits (IC) presents significant challenges with respect to manufacturability, reliability, cost, and power consumption. Recent work has therefore advanced the concept of “upscaling” through three-dimensional (3D) stacked ICs. Industry trends highlight the viability of 3D integration in actual products (e.g., the AMD Radeon R9 Fury X graphics card, Xilinx Virtex-7 2000T/H580T and Ultra-scale FPGAs). Flash memory vendors have announced multiple layers of memory in a single package, e.g., as many as 32

Physical Attacks: Implementation, Simulation, and Synthesis

Tue, 2017-08-29 15:54 -- root
Physical attacks on complex systems require ingenious attack implementations. Resilience against such attacks relies on efficient simulation, synthesis, and verification tools. This session starts with an efficient, high-resolution simulation method to automate electromagnetic side-channel leakage in cryptographic hardware. It also presents two papers on novel physical attacks: (1) fault injection attack on a deep neural network to disrupt the classification result and (2) a cache bank timing attack on AES to extract secret keys.

Modern Techniques for Challenging Verification Problems

Tue, 2017-08-29 15:54 -- root
This session presents a range of SAT-based techniques to conquer major challenges in pre-silicon, post-silicon, repair and functional timing. The first paper proposes a novel approach for SAT-based model checking using approximations. The second paper introduces an approach for improving the coverage of electrical bugs in post silicon validation. The third paper formulates the problem of patching sequential circuits in the presence of retiming and resynthesis.

ACM Student Research Competition Poster Session

Tue, 2017-08-29 15:54 -- root
Sponsored by Microsoft Research, the ACM Student Research Competition (SRC) is an internationally recognized venue enabling undergraduate and graduate students who are members of ACM and ACM SIGDA to:
•Experience the research world—for many undergraduates this is a first!
•Share research results and exchange ideas with other students, judges, and conference attendees.
•Rub shoulders with academic and industry luminaries.
•Understand the practical applications of their research.
•Perfect their communication skills.

Cross-Layer Efforts for Combating Computationally Hard Problems

Tue, 2017-08-29 15:54 -- root
Computationally hard (i.e., NP-hard) problems are quintessential to many electronic design automation problems, and are also at the heart of many decision, scheduling, error-correction and security applications. Their NP-hard nature makes solving them extremely resource demanding, either in terms of computation time or hardware components or energy.

Improving Manufacturability -- From Design through Mask Generation

Tue, 2017-08-29 15:54 -- root
Assuring manufacturability of present and future technologies and designs is crucial, and multiple methods are needed to achieve this. First, designs must better comprehend process constraints. The first paper effectively factors in implant-area constraints in multi-Vt designs, during mixed-cell-height place and route. Second, potential layout hotspots must be efficiently identified in a candidate design. The second paper achieves cluster count reduction during layout pattern classification using proposed heuristics.

Camouflaging and Logic Encryption

Tue, 2017-08-29 15:54 -- root
This session covers camouflaging and logic encryption attacks and countermeasures. Topics include attacks on decamouflaging sequential circuits without scan access, SAT-based attack on cyclic logic encryption, and a variety of novel countermeasure techniques for storing obfuscated master keys with quantifiable security and obfuscation of interconnects.

Advanced Caching and In-Memory Processing

Tue, 2017-08-29 15:54 -- root
This session presents four papers to advance the design of cache memories and take advantage of in-memory processing to accelerate applications. The first paper builds an efficient hybrid cache for multicore processors by exploiting value locality. The second paper explores cache bypassing and partitioning on GPUs. The third paper proposes a virtual persistent cache concept to remedy the long latency in Host-Aware Shingled Magnetic Recording (HA-SMR) drives. The final paper present a memristor-based in-memory processing for accelerating object recognition tasks.


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