2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

HDSLs: Domain Specific Languages for Hardware and SoC Design

Tue, 2017-08-29 15:54 -- root
Model Driven Architecture (MDA) is an Object Management Group (OMG) vision for the automation of software design that is almost 15 years old. Recently, a new version 2.0 was published, which takes care of the demand for an even higher level of flexibility. Companions of MDA are so called domain specific languages (DSLs). These languages differ from general purpose languages such as Java, C++ and Python as they are much smaller in terms of constructs and concepts and tailored to specific domains and to specific target hardware architectures.

Application Mapping and Estimation Methods for Heterogeneous Platforms

Tue, 2017-08-29 15:54 -- root
Two major challenges for wide adoption of heterogeneous platforms are accurate estimation of design metrics and high quality mapping of applications. The first paper discusses a novel SAT-based method for application mapping to CGRA platforms. The second paper improves cross platform power and performance prediction by neural networks. Another paper in the session addresses the shortcomings of performance estimation in HLS flows. The last paper presents a new methodology for dealing with big data in a streaming way.

Errors are Evil: Design for Reliability!

Tue, 2017-08-29 15:54 -- root
Multiple factors can cause circuits and memories to fail --- aging, stress, defects and layout imperfectness all play a role. This session aims to alleviate these reliability and yield challenges. The first paper presents a procedure for evaluating the performance of 3D-stacked wide-I/O DRAMs under process-induced stress. The second paper combines multiple ideas to implement a dynamic partitioning scheme in dense memories that can better address clustered stuck-at faults. The third paper presents a fast algorithm for electromigration-induced IR-drop degradation in an on-chip power grid.

Predictive Process Design Kit (PDK) to Accelerate Academic Research in VLSI Design and CAD

Tue, 2017-08-29 15:54 -- root
Academic research in VLSI design and CAD, especially for advanced technology nodes has been severely limited by the lack of quality process design kit (PDK). Most advanced technology circuit and CAD research employ either SPICE-only predictive technology models or scale 45nm OpenPDK libraries to sub-10 or 7nm node dimensions. These methods omit important effects such as layout-dependent middle-of-line (MOL) parasitics, BEOL parasitics, multiple patterning effects, etc.

Biochips, Neuromorphic and Stochastic Computing

Tue, 2017-08-29 15:54 -- root
This session discusses novel computing paradigms and applications. The first two papers propose methodologies for the design of novel biochip architectures and techniques for online error recovery for biochips. The third paper describes an implementation of an LSTM neural network on the IBM True North architecture. The final paper presents a novel random number generator for use in stochastic computing.

Right Timing for Power!

Tue, 2017-08-29 15:54 -- root
The session is dedicated to advances in static timing and power analysis, which are the key steps of modern design timing closure and signoff flows. The first paper attempts to combine the accuracy benefits of path-based analysis with the good performance of graph based analysis. The second paper of the session describes an advanced constraint-based methodology in power grid verification. The third paper proposes a general graph sparsification methodology, applicable to solving large power grids.

Advanced Routing Across Different Application Domains

Tue, 2017-08-29 15:54 -- root
To get the best out of technology scaling, and meet the application needs, routing needs to be looked at carefully. The papers in this session look at different approaches ranging from post-placement to routing stages to meet complex tradeoffs across different application requirements. We start the session by addressing the problem of leakage power in modern power gated systems on chip. Then, we address the 3D integration problem from a unified RDL routing approach.

How EDA Could Save the World (of Computing)

Tue, 2017-08-29 15:54 -- root
With the end of Moore's Law arriving soon, there is much concern for the future of computing. Rightly, much of the research community's focus has turned toward heterogeneous parallel architectures, whose application-specialized designs hold the promise to overcome the lost benefits of silicon dimensional scaling. In this talk, I will make the case that the future success of computing has less to do with "how" we design these architectures and more about "how much" will it cost to bring them to the market.

ACM/SIGDA Member Meeting

Tue, 2017-08-29 15:54 -- root

The annual ACM/SIGDA Member Meeting will be held on Tuesday evening from 6:45-8:30pm. The meeting is open for ACM SIGDA members to attend. Members of the Electronic Design Automation community who would like to learn more about SIGDA or get involved with SIGDA activities are also invited. Dinner

Automotive EDA: Constructing the Intersection of Silicon Valley and Motor City

Tue, 2017-08-29 15:54 -- root
The design and implementation of an automotive vehicle have become increasingly challenging, with growing functional complexity in scale and features, the adoption of more distributed and networked architectural platforms, and stringent demands on various design constraints posed by performance, fault tolerance, reliability, extensibility and security.

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