2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

Tue, 2017-08-29 15:54 -- root
Constrained optimization problems are at the heart of many decision, scheduling, error-correction and cyber security applications. Constrained optimization is also a major component in most fundamental EDA problems. Many constrained optimizations are NP-hard in nature, which makes solving them extremely resource demanding, either in terms of computation time or hardware components or energy. Given the importance of these problems, any improvements in efficiency in solving such problems are in great need. As an example, there is a world-wide competition taking place every two years, devoted to finding the best solvers for one of the representative NP-hard constrained optimization problems, i.e., Boolean Satisfiability (SAT).

Most of the efforts on improving solvers for constrained optimization problems aim at developing more effective search algorithms with the understanding that these algorithms would eventually be implemented on modern general-purpose digital computing platforms such as multi-core or many-core processors. Several researchers have investigated implementing such essentially digital algorithms on application specific integration circuits, hence achieving better performance, but at a higher cost. These approaches have been enjoying good success, as they readily benefit from the continuous improvements in CMOS technology that have been governed by Moore’s Law. However, with Moore’s Law coming to an end, exploring novel computational paradigms (e.g., quantum computing and neuromorphic computing) is more imperative than ever. Recently there has been increased interest in designing analog, or mixed-signal solvers for some specific NP-hard optimization problems based on continuous–time dynamical systems. Furthermore, a number of researchers are investigating approaches that exploit intrinsic properties exhibited by certain beyond-CMOS devices to solve NP-hard optimization problems.

The purpose of NAHO workshop is to bring together researchers who work on all these aspects employing various approaches for solving hard constraint satisfaction and optimization problems. The workshop will provide a platform for these researchers to exchange advances in each of their respective areas, compare and critique each other’s approaches, and forge new collaborative relationships. NAHO is a 1-day event including formal presentations followed by discussion panels and poster presentations by students or junior researchers. All the speakers will be invited.

If you are interested in presenting a poster, please contact Sharon Hu at shu@nd.edu. For more information about the workshop, visit naho.nd.edu
Event ID: 
45292177-734f-4ad7-aa20-37247a1820c1
Event Type: 
Workshop
Location: 
SSR
Event Time: 
Thursday, November 16, 2017 -
08:00 to 17:00
Session Number: 
6
Session Number Suffix: 
W
Session Number: 
6
confID: 
242