2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

Tue, 2017-08-29 15:54 -- root
This session brings together new advances in technologies and architectures that enable a new generation of highly efficient system-level optimizations that were previously not possible. The first paper conducts a comparison of performance and cost evaluation for traditional 2D monolithic SoCs, 2.5D passive interpose and 2.5/3D active interposer and evaluates their tradeoffs. The session goes on with a presentation based on a hybrid STT-RAM/SRAM register file exploiting the advantages of both technologies to enable an efficient warp scheduler that significantly improves system performance and energy efficiency. The third paper proposes a novel NoC architecture that allows a single-cycle multi-hop and thereby allows for a novel tradeoff between latency and energy-efficiency.
Event ID: 
ed5bf27f-25a4-43a9-9f3b-52391189355c
Event Type: 
Regular Session
Location: 
Salons B2 & C
Event Time: 
Wednesday, November 15, 2017 -
16:15 to 17:45
Session Number: 
10
Session Number Suffix: 
B
Session Number: 
10
confID: 
242