2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

Tue, 2017-08-29 15:54 -- root
Advances in gate level optimizations require complex trade-offs that include tool efficiency, design accuracy, and circuit timing. The first paper presents a fast Lagrangian relaxation based gate sizer. The second paper uses statistical testing to generate approximate circuits that provide error guarantees with high confidence level. The final paper describes a timing-driven optimization that makes use of a pre-computed restructuring choices.
Event ID: 
213ef382-aebd-4087-9d9a-4fb6284622b9
Event Type: 
Regular Session
Location: 
Salons B2 & C
Event Time: 
Tuesday, November 14, 2017 -
10:30 to 12:00
Session Number: 
5
Session Number Suffix: 
B
Session Number: 
5
confID: 
242