2017 International Conference On Computer Aided Design

The Premier Conference Devoted to Technical Innovations in Electronic Design Automation

November 13-16, 2017Irvine Marriott Irvine, CA

Tue, 2017-08-29 15:54 -- root
This session presents four papers to advance the design of cache memories and take advantage of in-memory processing to accelerate applications. The first paper builds an efficient hybrid cache for multicore processors by exploiting value locality. The second paper explores cache bypassing and partitioning on GPUs. The third paper proposes a virtual persistent cache concept to remedy the long latency in Host-Aware Shingled Magnetic Recording (HA-SMR) drives. The final paper present a memristor-based in-memory processing for accelerating object recognition tasks.
Event ID: 
b05eef12-0fd8-40a2-884b-fda4c9497cd3
Event Type: 
Regular Session
Location: 
Salon E
Event Time: 
Monday, November 13, 2017 -
10:30 to 12:30
Session Number: 
1
Session Number Suffix: 
A
Session Number: 
1
confID: 
242