SESSION 8E
TUTORIAL: TUTORIAL 4: Nanolithography and CAD Challenges for 32nm/22nm and Beyond
Organizer: David Z. Pan - Univ. of Texas, Austin, TX
The semiconductor industry is stuck at 193nm lithography as the main workhorse for manufacturing integrated circuits of 45nm and most likely 32nm nodes. On one hand, many novel approaches are being developed to extend the 193nm lithography, including immersion, double patterning, and exotic resolution enhancement techniques. On the other hand, next generation lithography, in particular, extreme ultra violet lithography (EUVL) is projected by ITRS as the main contender for technology nodes at or below 22nm, though significant challenges still exist from both technology and economy aspects. This tutorial will cover key nanolithography and CAD challenges with possible solutions for 32nm/22nm (and beyond?), from the underlying hardware/equipment perspectives (for double patterning, EUV, and so on), to the computational lithography aspects (extreme RET, inverse lithography, pixelated mask, etc.), and to the key EDA issues on nanolitho-friendly layouts (e.g., double patterning compliance layout, and so on).
Stephen Renwick is a Principal Engineer at Nikon Precision, Inc., where he has been part of the Advanced Technology Department for eight years. He is an active contributor/speaker to the lithography communty. His work currently focuses on the vital development of imaging solutions to further extend ArF immersion and dry lithography capabilities, as well as the introduction of Nikon's next-generation EUV systems. Steve holds a Ph.D. in atomic physics from Wesleyan University.
Vivek Singh got his Ph.D. from Stanford University in 1993. He started his career at Intel in the Technology CAD Department, and has since worked on many different aspects of lithography technology selection and optimization. He is currently a Senior Principal Engineer at Intel, and the Manager of the Computational Lithography Group, responsible for the development of all tools related to OPC, rigorous lithography simulation, and Double Patterning.
Judy Huckabay is a Manufacturing Products Architect at Cadence Design Systems. Judy has a BSCS from CSUH. She spent the last 19 years working in the EDA Industry at Cadence Design Systems. She has architected solutions in Physical Verification, Parasitic Extraction, RET and DFM solutions. Judy has 9 patents. She has been working on Double Patterning and RET solutions for the last 9 years. Judy has been a member of IEEE for over 20 years.
Vivek Singh - Intel Corp., San Jose, CA
Judy Huckabay - Cadence Design Systems, Inc., San Jose, CA
