| 3A.1* | Pre-Bond Testable Low-Power Clock Tree Design for 3-D Stacked ICs | |
| Speaker: | Xin Zhao - Georgia Institute of Technology |
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| Authors: | Xin Zhao - Georgia Institute of Technology Dean L. Lewis - Georgia Institute of Technology Hsien-Hsin S. Lee - Georgia Institute of Technology Sung Kyu Lim - Georgia Institute of Technology |
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| 3A.2 | Layout-Driven Test-Architecture Design and Optimization for 3-D SOCs under Pre-Bond Test-Pin-Count Constraint | |
| Speaker: | Jiang Li - The Chinese Univ. of Hong Kong |
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| Authors: | Jiang Li - The Chinese Univ. of Hong Kong Qiang Xu - The Chinese Univ. of Hong Kong Krishnendu Chakrabarty - Duke Univ. T. M. Mak - Intel Corp. |
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| 3A.3s | BIST Design Optimization for Large-Scale Embedded Memory Cores | |
| Speaker: | Tzuo-Fan Chien - National Taiwan Univ. |
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| Authors: | Tzuo-Fan Chien - National Taiwan Univ. Wen-Chi Chao - National Taiwan Univ. Chien-Mo Li - National Taiwan Univ. Yao-Wen Chang - National Taiwan Univ. Kuan-Yu Liao - National Taiwan Univ. Ming-Tung Chang - Global Unichip Corp. Min-Hsiu Tsai - Global Unichip Corp. Chih-Mou Tseng - Global Unichip Corp. |
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| 3A.4s | Operating System Scheduling for Efficient Online Self-Test in Robust Systems | |
| Speaker: | Yanjing Li - Stanford Univ. |
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| Authors: | Yanjing Li - Stanford Univ. Onur Mutlu - Carnegie Mellon Univ. Subhasish Mitra - Stanford Univ. |
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