It is widely recognized that process variation is emerging as a fundamental challenge to IC design in scaled CMOS technology; and it will have profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled with improvements in the manufacturing process, the industry is starting to accept the fact that some of the effects are better mitigated during the design process. Handling variability in the design process will require accurate and appropriate models of variability and its dependence on designable parameters (i.e. layout), and its spatial and temporal distributions. It also requires carefully designed test structures and proper statistical data analysis methods to extract meaningful models from large volumes of silicon measurements. The resulting compact modeling of systematic, random, spatial, and temporal variations is essential to abstract the physical level variations into a format the designers (and more importantly, the tools they use) can utilize. This workshop provides a forum to discuss current practice as well as near future research needs in test structure design, variability characterization, compact variability modeling, and statistical simulation.

Key topics of this workshop includes (but not limited to):
• Physics mechanisms and technology trends of device-level variations.
• First-principles simulation methods for predicting variability.
• Time-dependent variation and their interaction with other variation sources
• Compact modeling of variations in transistors and interconnect.
• Device and circuit level modeling techniques.
• Test structure design for variability.
• Variability characterization and bounding.
• Statistical data analysis and model extraction methods.
• Novel implementation and simulation techniques for dealing with variability.

Workshop website:  http://www.eas.asu.edu/~ycao/cvm/

Final Program: http://iccad.com/2009/PDFs/CVMT2009_program_rev.pdf