Registration - 7:00am - 6:00pm (Gateway Foyer) Speaker's Breakfast - 7:30am - 8:30am (Donner/Siskiyou Ballroom) AV Practice Rooms - 7:00am - 6:00pm (Chardonnay, Riesling, Zinfandel)
Tutorial 1
Designing for Uncertainty: Addressing Process Variations and Aging Issues in Digital Systems
Session 1A
Fast and Accurate System Estimation, Evaluation, and Optimization
Session 1B
Manufacturing-Aware Design
Session 1C
Analog and Mixed Signal Verification and Optimization
Tutorial 2
Reliability Analysis and Optimization at System Level: A Straddle Between Complexity and Accuracy
Session 2A
Design-Aware Manufacturing
Session 2B
Advances in Embedded Systems and FPGA Synthesis
Session 2C
Enhancing Test for Relay and Opens Under Power Sensitive Conditions
Tutorial 3
Analog Challenges in Nanometer CMOS and Digitalization of Analog Functionality
Session 3A
Advanced Scheduling for Memory Systems
Session 3B
Making Critical Decision on Power in Physical Synthesis
Session 3C
Advances in Yield and Quality Analysis