Wednesday, November 4, 2009
Schedule
Monday | Tuesday | Wednesday
| Registration - 7:00am - 1:00pm (Bayshore Foyer) Speakers’ Breakfast - 7:30am (Siskiyou Ballroom) |
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| Oak Ballroom | Fir Ballroom | Pine Ballroom | Cedar Ballroom | Donner Ballroom | |
| 8:30 10:00 |
Session 8A Yield Estimation and Optimization for SRAMs |
Session 8B Thermal Modeling and Analysis at Chip and Platform Levels |
Session 8C Analytic Placement |
Session 8D Performance and Power Issues in Embedded System-Level Design |
Session 8E Tutorial: Biological Circuits and Systems |
| Coffee Break: 10:00 - 10:30am | |||||
| 10:30 12:30 |
Session 9A Statistical Simulation and Optimization of Serial Link and Wordlength |
Session 9B Parasitic Extraction, Modeling, and Reduction Techniques |
Session 9C Advanced Boolean Techniques in Logic Synthesis |
Session 9D Tutorial: Global Routing Revisited |
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Lunch: 12:30 - 1:30pm |
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Workshop Reception: 5:30 - 6:30pm |
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