Registration - 7:30am - 6:30pm (Bayshore Foyer) Technology Fair 10:00am - 6:00pm (Gateway Foyer) Speakers’ Breakfast - 7:30am (Siskiyou Ballroom)
Session 1A
Functional Verification
Session 1B
Advances in Routing
Session 1C
Tutorial: Design for Manufacturability: Current Practice and Future Directions
Session 1D
Scheduling Techniques for Low Power
Session 1E
Special Session: Resilient Computing
Session 2A
Advances in Test Efficiency
Session 2B
Advances in FPGA Synthesis and Trustable Silicon
Session 2C
Design Automation for Biological Systems
Session 2D
Analysis and Mitigation of Transient and Permanent Failures
Session 2E
Tutorial: An Introduction to Satisfiability Modulo Theories
Session 3A
Emerging Topics in Test and Reliability
Session 3B
Timing Closure and Design Robustness
Session 3C
Routing in Alternative Technologies
Session 3D
Emerging Design and Memory Technologies
Session 3E
Tutorial: Embedded Processors, Methods and Applications: Computer Architects Perspective